Smit Center Shanghai

Please acknowledge which events you will attend: BaoShan Campus , Shanghai University
Short Course Registration Fees		On-Site	Venue
30 June 2004 Wednesday	□Itsuo Watanabe, 08:30～12:30	$100	Room 314,A Building
	□James E. Morris, 13:30～17:00	$100	Room 314,A Building
	□Dr Lawrence Wu, 08:30～12:30	$100	Room 315,A Building
	□Dr. Jie Xue, 13:30～17:00	$100	Room 315,A Building
	□Prof. C.P. Wong, 08:30～12:30	$100	Room 316,A Building
	□Dr. Li LI, 13:30～17:00	$100	Room 316,A Building
	□Torsten Wipiejewski, 08:30～12:30	$100	Room 317,A Building
	□Dr Hans Grönqvist, 13:30～17:00	$100	Room 317,A Building
	□Dr Wei Koh, 08:30～12:30	$100	Room 318,A Building

1. Recent Trend of Packaging Technologies using Anisotropic Conductive Films

By Itsuo Watanabe, Display Materials Division, Hitachi Chemical Co., Ltd., 1150 Goshomiya, Shimodate, Ibaraki 308-8524, Japan

Course Outline

Today, LCDs are widely used in various display applications, such as note PCs, monitors, TVs, cellular phones, audiovisual products, multimedia products, etc. Interconnection technologies using ACFs which consists of conducting particles dispersed uniformly in adhesives play an important role in LCD module packaging which requires high resolution, light weight, thin package and low consumption power. When we see LCD module packaging using ACFs, it can be seen that most of the LCD modules larger than 10 inches are assembled by interconnecting a TCP with a driver IC and a glass panel using ACFs. In addition, it can be seen that more and more companies are using COG(Chip on glass) with ACFs for small size of LCD modules such as cellular phones since the early 1990s. Recently we can also see that COF technologies using ACFs are becoming of much interest to realize finer pitch capability and make LCD modules thinner, lighter and smaller. In this seminar, recent packaging technologies for driver ICs in flat panel displays are discribed.

Since ACFs are able to provide attachment, electrical interconnection and encapsulating at the same time, ACF interconnection procedures are expected to use as interconnection technology for flip-chip package. In this seminar, advanced semiconductor package using ACFs will be also introduced.

Itsuo Watanabe, a Senior Manager, Goshimiya Works of Hitachi Chemical Co., Ltd.. He has been employed by Hitachi Chemical since 1982. He has been responsible for developing anisotropic conductive films for flat panel displays and flip-chip technologies(chip on glass, chip on flex and PWB). He had been a visiting scientist of Massachusetts Institute of Technology (Department of Materials Science and Engineering) from 1987 to 1989. He has also studied on conducting polymers, organic optical recording materials and polymeric materials for optical communication. He received his BS and MS in Chemistry from Utsunomiya University and PhD in Polymer Science from Kyoto University. His doctoral research was concerned on syntheses, thin film formation, electrical and optical characteristics of conducting polymers.

Dr. Watanabe is a vice chairman of the organizing and the technical committee of the International Conference on Electronics Packaging. In 2003, Dr Watanabe received the Award of the Society of Polymer Science, Japan for the Research on Anisotropic Conductive Adhesive Films.

By James E. Morris, Department of Electrical & Computer Engineering, Portland State University, P. O. Box 751, Portland, OR 97207-0751, USA.

Course Outline

The drive towards no-lead soldering solutions has also created interest in polymeric adhesive alternatives. The most traditional form of electrically conductive adhesives (ECAs) is the ICA, formed by loading metal into a traditional adhesive. As with all engineering solutions, this one has pros and cons, and to assess these requires full understanding of the basic properties of the materials.

The course will cover the basic concepts of the structure-related properties of ICA materials, and test results which identify failure modes. The course objectives include the development of an understanding of the primary principles of process and properties, with recognition of what is still not understood, and hence how to achieve reliability.

James E. Morris is Professor and Chair of Electrical & Computer Engineering at Portland State University, Oregon, Professor Emeritus at the State University of New York at Binghamton, and an IEEE Fellow. His B.Sc. and M.Sc. (with 1st Class Honors in Physics) degrees are from the University of Auckland, New Zealand, and the Ph.D. in Electrical Engineering is from the University of Saskatchewan, Canada.. He served six years as EE Department Chairman at Binghamton, and was the first Director of its Institute for Research in Electronics Packaging. Professor Morris was Treasurer of the IEEE Components, Packaging, and Manufacturing Technology Society from 1991 until 1997, Vice-President for Conferences from 1998 until 2003, and is now an IEEE-CPMT Distinguished Lecturer. He is an Associate-Editor of the IEEE Transactions on Components and Packaging Technology, with responsibility for Adhesives, and has edited three books on electronics packaging. He was General Chair of the Adhesives in Electronics conference in 1998, and of the 2001 International Symposium & Exhibition on Advanced Packaging Materials, and will Chair Polytronic 2004 in Portland this year. His research activities are currently focused on electrically conductive adhesives and the electrical conduction mechanisms in discontinuous thin metal films, with application to single-electron transistor nanoelectronics. He is also actively involved in the promotion of international educational exchanges, and in Internet education.

By Dr Lawrence Wu, Department of Physics and Materials Science, City University of Hong Kong

The use of lead-tin solder alloy in electronics manufacturing has been wide, from the plated-through-hole printed circuit board (PCB) assembly to flip-chip bumps. The issue of environmental protection legislation in Japan, Europe and possibly the US has imposed some “deadlines” for electronics manufacturers to follow, to convert their manufacturing processes to lead-free ones. The International Printed Circuit (IPC) Association of the US had recently issued recommendations for manufacturers, by naming the Japanese adopted tin-3.0wt%silver-0.5wt%copper (Sn-3.0Ag-0.5Cu) alloy and the NEMI adopted Sn-3.9Ag-0.6Cu one. This is seen as a further impetus for manufacturers and researchers to unify their approaches in lead-free manufacturing and product development. Despite this, manufacturers should aware that these two named alloys may still provide problems for certain products. This course has three main directions. First, the main properties of the main lead-free solders will be introduced. Secondly, the potential problems for using these alloys, such as solderability and reliability issues such as electromigration and interfacing problems with substrate, e.g. PCB, finishes will be outlined. Thirdly, the latest ongoing efforts in the research world in tackling these issues will be introduced.

Dr Lawrence Wu graduated from the University of Bristol, U.K. in Aeronautical Engineering with First Class Honours. He also obtained his PhD from the same university. He has been working at City University of Hong Kong (CityU) since 1987. He is currently an Associate Professor at the Department of Physics and Materials Science. He is also the Deputy Director of the Centre for Electronic Packaging and Assemblies, Failure Analysis and Reliability Engineering at CityU.

Dr Wu has been conducting research on lead-containing and lead-free alloys for a number of years, in particular on surface mount solder joint strength, lead-free solder development, and the formation and analysis of lead-free solders doped with rare earth elements.

Apart from lecturing on the courses of “electronic packaging and materials” and “failure analysis and cases studies” at senior undergraduate and postgraduate levels at CityU, he is also active in conducting failure investigation/analysis and materials characterization related to industries.

4. Introduction to Ball Grid Array (BGA) Technology: Design, Assembly, and Reliability

Driving by both wireless and communication applications, Ball Grid Array (BGA) technology has been widely used because it offers many advantages such as board real estate saving, high assembly yield, and high electrical performance. The objective of this course is to review different BGA package structures, bard level assembly, as well as interconnect reliability. Technical challenges of developing and implementing BGA technology will also be discussed.

Jie Xue is currently the manager of manufacturing technology group at Cisco Systems, Inc. Her team is responsible for development of advance packaging technology, packaging assembly technology, and packaging interconnect reliability for high performance router switch products. Prior to joining Cisco in 2000, Jie held several management and engineering positions in Motorola Inc. for over eight years, working on R&D and product development in the areas of automotive electronics, displays, high density interconnect PCB, optical interconnect, and wireless products. Jie obtained Ph.D. in material science and engineering from Cornell University, and BS from Tsinghua University. Jie is a member of IEEE, IMAPS, and SMTA.

5. Polymers for Electronic and Photonic Packaging: Materials, Process and Reliability: Part I-The Fundamentals of Packaging and Materials Science & Engineering

By Prof. C.P. Wong, School of Materials Science and Engineering, and NSF -Packaging Research Center, Georgia Institute of Technology.

• Fundamentals of Polymers and their Physical and Mechanical Properties and Measurements

• Overview of Inorganic and Organic Polymers for Electronic and Photonic Packaging

- Epoxies, Silicones, Polyimides, Silicone-Polyimides, Polyurethanes, Benzocyclobutenes, Parylenes, BT resins, Sycars, Polyesters, High Temperature & Liquid-crystal polymers, Low k, low loss and nano- functional and-foam materials, OLED.

Dr. C.P. Wong is a Regents’ Professor(highest ranking professor) of Materials Science and Engineering and a Research Director of the NSF-funded Packaging Research Center at the Georgia Institute of Technology. His research interests lie in the area of polymeric materials (organic and inorganic), in particularly, low-cost, high-performance materials and manufacturing processes. Prior in joining Georgia Tech in 1996, he was with AT&T Bell Laboratories for 19 years and was elected an AT&T Bell Labs Fellow in 1992. He holds over 40 U.S. patents, numerous international patents, and has published over 400 technical papers and 350 presentations in the packaging related areas. Dr. Wong received the B.S. degree in chemistry from Purdue University, the Ph.D. degree in chemistry from Penn State University, and was a Postdoctoral Fellow with Nobel Laureate Prof. Henry Taube at Stanford University. He received many Awards from the IEEE, IMAPS, AT&T Bell Labs, and the Georgia Tech(GT). Among those the GT 1999 Outstanding Research Program Award, the 1999 NSF-ERC Packaging Research Center Faculty of the Year Award, the IEEE EBA Award in Continue Education in 2001, the Exceptional Technical Contribution Award in 2002 and the Henry Toops Award in 2003. He serves on the Editorial Boards of the IEEE Trans. on Components, Packaging Technology, the Chip Scale Review and he is the editor-in-chief of the John-Wiley Encyclopedia on Smart Materials. He is a fellow of IEEE, AIC and Bell Laboratories and is a member of the National Academy of Engineering of the USA.

6. Challenges in Module Assembly and System in Package (SiP): Case Studies and Development in embedded passives

This workshop provides fundamental principles, engineering data, and cutting edge information on the latest development and research results in module assembly technology. It will have a special focus on the current trend and challenges facing by the industry. Experience of using passives and embedded substrates in module assembly to increase electrical performance and reduce size in mobile and advanced electronics will also be discussed.

Dr. Li LI: After receiving her Ph.D. degree in electrical engineering from the State University of New York at Binghamton in 1995, Dr Li joined Motorola Semiconductor Products Sector in Tempe, AZ. She has worked on various areas of packaging materials and process development, including flip chip interconnect and chip scale package development, Sn-Pb and Pb-free solder wafer bumping, and anisotropically electrically conductive adhesives interconnects. Being a Distinguished Member of Technical Staff in Motorola’s Semiconductor Products Sector in Tempe, AZ., she is currently working on RF module development with embedded passives and flip chip in RF module development, component models for design libraries to facilitate effective RF module design flows, embedded passive filter and matching network design and simulation, and integrated passives design and simulation on organic substrate and on BiCMOS SiGe substrate. Her main achievements are:

• IEEE CMPT Society “Outstanding Young Engineer Award” for the year 2002 (co-winner)

• Co-author of a book chapter on “Curing of Isotropic Electrically Conductive Adhesives,” in Conductive Adhesives in Electronics Packaging (edited by Johan Liu)

By Torsten Wipiejewski, Ph.D, VP Photonics Applications, ASTRI(torsten@astri.org)

· Introduction: modern optical transmission systems from short distance to long-haul

Dr. Torsten Wipiejewski is currently Vice President of Photonic Applications at ASTRI in Hong Kong. His main interest is ultra low cost photonic components for information transmission and sensing. Before joining ASTRI in February 2003, Torsten Wipiejewski was Director of Advanced Technology and Program Manager at Agility Communications in Santa Barbara, California. Until the year of 2000 he was the General Manager of the Optoelectronic Components Group of Infineon Fiber Optics in Munich, Germany. His responsibility included R&D and production of VCSELs and edge emitting lasers. He joined the Fiber Optics division in 1996. Torsten Wipiejewski received a “summa cum laude” Ph.D. degree for his work on vertical-cavity surface-emitting lasers (VCSELs) from the University of Ulm, Germany in 1994 and a M.Sc. degree in Electrical Engineering from the Technical University of Braunschweig, Germany in 1990. He spent two years as a post-doctoral researcher at the University of California at Santa Barbara and at the University of Ulm as a manager of a joint European R&D project.

Dr. Wipiejewski is the Chair of the ECTC2004 Optoelectronics Program Committee. He has been a member of the ECTC Optoelectronics Committee since 1996. Torsten is also program committee member of SPIE Photonics West 2003 and EPTC2003. He is a member of IEEE LEOS and CPMT and has authored or co-authored more than 100 publications and over 20 patents. He was awarded Agility’s “Patent Award” in 2001 and 2002, the Infineon’s “Inventor of the Year Award” in 1999, the “Project Innovations Award” of the Siemens Semiconductor Group (now Infineon) in 1999, and the “Best Ph.D.-Thesis Award” in 1994.

By Dr Hans Grönqvist，SMIT Center & IVF Division of Electronics and Microsystem Integration hans.gronqvist@ivf.se

Microwave design of electronic equipment is different from conventional electronic design due to the wave nature of the electronic signals. The wave length of these signals are often smaller than the physical dimensions of the device to be designed which lead to special design methods and require the use of dedicated CAD software packages.

In principle, everything can be designed using the well known Maxwell´s equations in combination with reasonable boundary conditions. Indeed, some CAD packages use this approach but in general this method is time consuming and require large amounts of computation power. The common approach is to use equivalent circuits consisting of ideal passive and active components. These equivalent circuits are built by the aid of computer simulations and measurements. The result is that each component used in a design is built up by a number of ideal components. A surface mounted resistors could then be represented by maybe six ideal passive components where at least one of them is an ideal resistor. The same method is used for all other parts of a design like transmission lines, coupled lines, via holes etc. In addition to the models of the components there is another major difference in microwave design which is due to the possibility of designing circuits using specific microwave components like couplers, hybrids, isolators and other. Unique functionality can be built into the devices that have no similarity for low frequency designs.

The course covers the subjects: wavelength、impedance、material properties、transmission lines、CAD tools、manufacturing issues、substrate materials、MMIC and MEMS、semiconductor devices (FET, HEMT, pHEMT, HBT,...) and more.

Hans Grönqvist was born in Pernå in Finland April 5 1958. He received his Masters degree in Engineering Physics, 1987, the degree Licentiate of Engineering in 1990 and the Ph.D. degree in 1994, all from Chalmers University of Technology in Göteborg, Sweden.

From 1994 to 2001 he worked as a microwave design engineer at Saab Ericsson Space on frequency converter programs for The European Space Agency and for customers like Hughes Space and Communications in USA. He also worked as project manager for future technologies for space applications at the Ka-band, (26 – 40 GHz).. Apart from the normal duties he also developed manufacturing and design technologies for these communication systems.

During 2001 to 2003 he worked at Saab MicroTech as a project manager in RF and Micro Systems with special responsibilities regarding RF-MEMS applications.

From 2003 he is employed at IVF AB in Mölndal, Sweden, and is responsible for the EMC facilities at IVF in Mölndal, Kista and Malmö. Current research involves manufacturing technologies for high frequency applications. He is a lecturer at Chalmers University of Technology in microwave design and packaging technologies.

9. Low Cost, High Volume Packaging Technology Update—From Leadframe to Wafer Level Packaging and 3-Dimensional Stacking

Instructor: Wei Koh, Kingston Technology Company, Fountain Valley, CA (wayne_koh@kingston.com), 714-427-3531

This workshop will review the current low cost, high volume mainstream semiconductor packages that are used in most of today’s electronics devices, for applications in computing, consumer electronics, and communications. The design, assembly and application of these packages and their advantages are described. Some examples of the selected packages, particularly those used in today’s memory cards such as Compact Flash cards (CF), Secure Digital cards (SD), and Multimedia cards (MMC) will be reviewed.

First, the leadframe packages represented by TSOP—thin small outline packages and its variations, type I and II, shrink TSOP, etc are discussed in detail. Newer package designs such as micro-leadframe (MLF), quad flat no lead (QFN) are included next. CSP packages using either flex and laminate substrates packages, including various FBGA, VFBGA, TFBGA designs are described.. A number of recent wafer level packaging (WLP) designs will also be reviewed. Finally, 3-Dimensional stacking—both die stacking and packaging stacking are discussed and their respective pros and cons in terms of form factor, performance, test and cost considerations are reviewed.

Wei Koh is Sr Director of Advanced Technology at Kingston Technology Company in Fountain Valley, CA. He has worked in the microelectronics industry for over 20 years. Prior to Kingston, he held various engineering management and research positions at Motorola and Northrop Grumman Corporation, respectively, in the US. In the 1980’s, he pioneered the use of flip chip bumping, high-density, 3-dimensional chip and module stacking, and high density interconnect (HDI) microvia substrate fabrication process. He has published over 70 articles and received over 20 US patents.

Dr Koh received his MS and PhD in Chemical Engineering from Cornell University, and BS Chemical Engineering from University of Washington. He is a member of IEEE CPMT, SMTA, IMAPS.

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