Smit Center Shanghai

Invited Talk 9: New Developments in Stacked Die CSPs

Speaker： E. Jan Vardaman, Linda Matthew， TechSearch International, Inc. 4801 Spicewood Springs Road， Suite 150， Austin, Texas 78759. tsi@techsearchinc.com

Abstract: The market for stacked die and stacked packages is driven by portable applications that require extremely small form-factors. Stacked die packages continue to see double digit growth. Almost every mobile phone and digital camera contains at least one stacked die CSP. Stacked die packages are also found in personal digital assistants (PDAs). While much of the volume has been in the two die stacked package, an increasing number of stacked die packages with three, four, or five die are shipping. In addition, Fujitsu Microelectronics, ChipPAC, and Intel are offering eight die stacked CSPs—some with interposers between the die.

The majority of packages shipping today are wire bonded, but flip chip is on the roadmaps of both semiconductor makers and IC package contract assembly houses. While most of the stacked die packages shipped historically are memory (flash and SRAM), packages containing logic devices are also increasingly moving into production.

Among the advantages of stacked solutions include smaller form factor, fast turn-time, and low NRE costs (compared to a single die design). The key challenges of stacked die products include both logistical and engineering issues. Issues related to die include wafer thinning, bare die, known good die (KGD), die attach and wire bond, and thermal dissipation. One solution to the bare die or KGD problem is to stack packages that are tested. Some of these packages may contain more than one die. Several configurations from companies including Intel and Fujitsu are in production.

Biography of Speaker:

E. JAN VARDAMAN received her B.A. in Economics and Business from Mercer University in 1979 and her M.A. in Economics from the University of Texas in 1981. She worked on the corporate staff of Microelectronics and Computer Technology Corporation in Austin, Texas where she analyzed international developments in semiconductor packaging and assembly. In 1987 she founded TechSearch International, Inc., providing licensing and consulting services in semiconductor packaging and is the president.

She is the editor of Surface Mount Technology: Recent Japanese Developments, published by IEEE. She is a columnist with Circuits Assembly magazine, and author of numerous publications on emerging trends in semiconductor packaging and assembly. She served on the NSF sponsored World Technology Evaluation Center (WTEC) study team involved in investigating electronics manufacturing in Asia. She is a member of IEEE’s CPMT society, IMAPS, and SEMI. She has been elected to the IEEE CPMT Board of Governors. In 1991 she received a technical contribution award for an outstanding technical lecture delivered at the SHM International Internepcon Joint seminar held on January, 22, 1991. She has served on the program committee for numerous IEEE conferences and workshops including the International Electronics Manufacturing Technology (IEMT) Symposium, the IEEE Computer Packaging Workshop in Santa Cruz, and the Electronics Components and Technology Conference (ECTC). She was the Vice Chair of the IEEE CPMT International Electronics Manufacturing Technology Symposium in 1995 and the General Chair in 1996. In 1997 she received an appreciation award for the many years of technical guidance and management provided to the IEMTS. She served as the U.S. liaison to the IEMT Japan conference from 1989 until its merger with IMC, where she continues her liaison duties. She served on the board of directors of IEPS and worked on the merger of IEPS and ISHM to create a combined society and received an appreciation award in 1997. She has been a course instructor at the ECTC since 1995.

Jan’s specialty is analyzing international developments in the field of semiconductor packaging and assembly. She has been an invited speaker for IEMT/IMC in Japan, IMAPS/Nordic in Finland, Singapore, the 30^th Anniversary of IMAPS France, and the opening of the Fraunhofer Institute in Berlin, Germany. She has authored more than 100 technical papers and made more than 90 presentations worldwide.

Invited Talk 10: Next Generation packaging technology for high performance ASICs

Speaker: Mark Brillhart, Cisco Systems, Inc., mbrillha@cisco.com

Outline of Speech:

As the data rate of high performance internet router systems continues to increase, meeting the challenges for high speed electrical performance pushes ASIC packaging technology for higher silicon integration, higher I/O density, and better thermal power dissipation. At the same time, high availability telecommunication products also require excellent reliability to be maintained not only at the ASIC package and card assembly level, but also at the final product system level. This presentation will review the trends and challenges of high I/O ASIC flip chip packaging, from the aspect of wirebility, electrical, thermal and mechanical. Issues on interconnect reliability raised by continuously increased Si die size, implementation of Cu Low-k silicon technology, and thermal dissipation will be discussed. Additional challenges at the system level to integrate high I/O ASIC into new products, such as PCB routing, flexibility and fast time to market for ASIC update, high speed signal integrity, and product reliability will be reviewed. Finally, technical trends of utilizing daughter card, module, and system in package (SIP) will be discussed.

Biography of Speaker:

Mark Brillhart is currently the Director of Hardware Reliability at Cisco System Inc. His team is responsible for packaging, printed circuit boards, assembly technology and lead free development and deployment. Mark joined Cisco in 1999, first as a technical lead and later as the manager of the Interconnect Reliability and Electronic Packaging teams. Mark has also led the Technology Council Roadmap team and the Process Development team. Prior to joining Cisco, Mark held several key management and engineering positions in R&D at Hewlett-Packard and at medical startups. Mark has graduate degrees in Materials Science/Polymers from the Massachusetts Institute of Technology and Mechanics from the University of Illinois.

Invited Talk 11: Reliability Predictions for High Density Packaging

Speaker: C. Bailey， Computing and Mathematical Sciences, University of Greenwich, Greenwich, London SE10 9LS

Outline of Speech:

An accurate prediction of the reliability of a newly designed high density microsystem product, before it is manufactured, is obviously highly desirable for many organisations. This is particularly the case in the packaging of the device where a large percentage of product failures can arise. Reliability predictions originated in the early years of the electronics industry. Originally these predictions were based on historical field data which has evolved into industrial databases and specifications such as the famous MIL-HDBK-217 standard, plus numerous others. Unfortunately the accuracy of such techniques is highly questionable especially for newly designed packages.

Today a more robust approach to reliability prediction for electronic packaged products, based on the so-called physics-of-failure methodology, is gaining acceptance. This approach combines accelerated testing, failure analysis, multi-physics modelling and optimisation technologies to understand the root cause of failure and estimate acceleration factors and life.

This paper will discuss the numerous reliability prediction techniques as used for high density packaging. Focus will be placed on the physics-of-failure methodology and examples of reliability prediction for flip-chip components will be presented. The paper will also highlight future trends in reliability prediction and the challenges these predictions face as we go to ever smaller length scales and introduce new greener materials.

Biography of Speaker:

Professor Chris Bailey holds a Ph.D in Mathematical Modeling and an MBA in Technology Management. After completing his Ph.D in 1988 he joined the Metallurgical Engineering and Materials Science Department at Carnegie Mellon University, USA. In 1991 he returned to the UK joining the Center for Numerical Modeling and Process Analysis at the University of Greenwich.

Professor Bailey and his research team are providing design tools and expertise for reliability predictions and process analysis to electronics manufacturing companies, both in the UK and internationally. He also lectures on the techniques and benefits of computational modeling to students at post-graduate level, and design engineers from industry. Professor Bailey has published over 120 refereed papers on computational modeling and its application to electronic product design, assembly, packaging and reliability.

Professor Bailey is a member of IEEE, IEE, TMS, the Society for Industrial and Applied Mathematics (SIAM), and a Fellow of the Institute for Mathematics and its Applications (IMA). He is also a UK committee member of IMAPS and a member of the EPPIC (Electronics and Photonics Packaging and Interconnection) Faraday Partnership in the UK.

Invited Talk 12: Review of Memory Device Packaging —From Leadframe Packages to Wafer Level Packages

Speaker: Wei Koh, Kingston Technology Company, Fountain Valley, CA (wayne_koh@kingston.com), 714-427-3531

Outline of Speech:

The digital revolution has taken the consumer electronics by a storm in just two-short years. Portable and handheld electronics devices now have insatiable appetite for digital storage. Hence, memory cards in the form of USB Drive (U-Drive), Compact Flash (CF), Secured Digital (SD), Memory Stick, and multimedia card (MMC) are now proliferating in the market. Moreover, the volatile memory Dynamic Random Access Memory (DRAM) for PC and notebook computing and gaming are also increasing in density and speed. With all these improvement, the memory device packaging technology is also evolving rapidly, from the traditional leadframe packages to smaller chip scale packages (CSP) and wafer level packages (WLP). This paper will cover the four major topics below:

1. Review of the DRAM packages and their applications--DRAM packages are used primarily in the fabrication of DIMM modules that are inserted to the motherboards in PC and notebook computers. With newer DRAM technology in double date rate (DDR) and its second generation, DDR2, to be deployed this year, the clock rate is much higher and the number of I/Os increasing. Packages therefore are changing from the leadframe TSOP type 2 to faster CSPs such as fine pitch BGA (FBGA).

2. Review of the flash memory card packages—Non-volatile memory flash and SRAM packages are generally smaller and have had lower density of 256Mb and below. But more recently high density (512Mb) and hence larger flash devices are more common. The conventional package TSOP type 1 may become inadequate to meet new performance demands and the form factor for miniaturization. Alternative new packages such as VFBGA CSP are described.

3. Stacking—Three-dimensional stacking have now been widely utilized to increase the memory density and saving weight and space. The two main options for stacking—die stack and package stack, each has its own advantages and concerns. The selection criteria and suitable applications for both the DRAM DIMM modules and various flash memory card formats are discussed in detail.

4. Future trends and conclusion—The convergence of packaging technology for the computing and consumer electronics is apparent under the same market and technology drivers—form factor miniaturization, lightweight, low profile, high speed, and high performance. Packaging for high-density memory devices is moving toward faster and smaller CSP packages, with the technology and processes for wafer level CSP and wafer level 3-dimensional stacking emerging in the horizon.

Biography of the Speaker:

Wei Koh is Sr Director of Advanced Technology at Kingston Technology Company in Fountain Valley, CA. He has worked in the microelectronics industry for over 20 years. Prior to Kingston, he held various engineering management and research positions at Motorola and Northrop Grumman Corporation, respectively, in the US. In the 1980’s, he pioneered the use of flip chip bumping, high-density, 3-dimensional chip and module stacking, and high density interconnect (HDI) microvia substrate fabrication process. He has published over 70 articles and received over 20 US patents.

Dr Koh received his MS and PhD in Chemical Engineering from Cornell University, and BS Chemical Engineering from University of Washington. He is a member of IEEE CPMT, SMTA, IMAPS

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