Invited Talk
5: Diamond Film/Alumina Composites Used as the Packaging Material in
Integrated Circuits with Ultra-High Speed and High Power
Speaker:
Yiben Xia, Linjun Wang, School of Materials Science and Engineering,
Shanghai University, Shanghai 20180, Email:
ybxia@mail.shu.edu.cn. Tel: 86-21-69982439
Abstract:
We
report the properties of the diamond film/alumina composites that were
thought of as promising substrate materials for integrated circuits
with ultra-high speed and high power. The compressive stress in
diamond films formed by hot filament chemical vapour deposition is
reduced by implantation of carbon ions into alumina substrates before
the deposition of diamond films. It is found that the stress in the
diamond films decreases linearly with the increment of the C+
implantation dose. The measurement results of dielectric properties of
diamond film/alumina composites show that the coating of CVD diamond
films could effectively reduce the dielectric constant of the
composite. The carbon ions implantation into alumina substrates prior
to the diamond deposition can reduce the dielectric loss of the
composite from 5¡Á10-3 to 2¡Á10-3, and can make
the composite have better frequency stability. The thermal
conductivity of composites could be obviously increased by coating CVD
diamond film. The composite has a dielectric constant of 6.5 and a
thermal conductivity of 3.98W/(cm¡ÁK)
when the thickness of diamond film is up to 100mm.
Biography of
Speaker:
Xia Yi-Ben, a Professor and Doctorate Supervisor, is devoting himself
to Microelectronic Materials & Devices, mainly involving Functional
Thin Film Materials, Diamond Films & Related Devices.
He was graduated from Fudan University majoring semiconductor physics
in 1965, and got the master degree majoring infrared semiconductor
from Chinese Academy of Sciences in 1981. He was a visiting scholar to
pursue advanced studies in Physics Department, Universitaet Wurzburg /
Germany over two years (1985-1987), Guest Professor in Fraunhofer Thin
Films and Surface Engineering Institute (Fhg-IST) /Germany (1996-1987)
and a Guest Professor in Materials Science Institute, Tohoku
University/Japan (1998-1999).
Now he is the Dean of School of Materials Science & Engineering in
Shanghai University, the Memberships of Chinese Electronics Society,
Chinese Optical Materials Society and Shanghai Semiconductor Materials
Society. Now the projects undertook are Infrared properties and
interfaces research of DLC ( Shanghai Natural Science Foundation),
Selected growth (development) at cell places by DPLF (a key project of
Shanghai Education Science Committee) and High-resolution X-ray
imaging ¡ª study of the micro strip gas chamber (National Natural
Science Foundation of China).
Invited Talk 6:
Embedded
Passives in Organic Substrate for RF Module and Assembly
Characterization
Speaker:
Li
Li, Semiconductor Products Sector, Motorola, Inc.,2100 E. Elliot Rd.,
MD: EL725, Tempe, AZ 85284, USA.
L.Li@motorola.com, Tel: 480-413-6653
Outline of
Speech:
More
functionality are being integrated in RF modules for both mobile phone
and other wireless applications. For example, a RF front-end power
amplifier (PA) module of GSM/GPRS mobile phone could have multiple
transmit-side power amplifier die, with integrated inter-stage and
output matching circuitries, couplers, power level detector and
control, filter, and transmit/receive switches, and various surface
mount (SMT) passive components to support functions. A BluetoothTM
RF front-end transceiver module comprises the RF transceiver die, its
external matching components, switches, filters, and other components
to fulfill the complete RF radio function, which can be used for
short-range communications in cellular phones, PDAs, and computer
network applications. These RF PA modules are typically assembled in
array panels, and over molded in panel form, and then singulated to
individual modules.Both LTCC (Low Temperature Co-fired Ceramic) and
organic substrate can be used for RF modules, driven by module cost
and size reductions. The paper will focus on embedding passives in
organic substrate, which is in general more cost effective. A band
pass filter (BPF), balun, matching network, and decoupling caps were
embedded successfully in the organic substrate, which dramatically
reduced module size and cost, and resulted in competitive size
modules, compared to LTCC, with less cost.
Characterization of module assembly and packaging material impact on
RF performance of the PA module is important to optimize the design
and maximize electrical performance. The paper will review the studies
on the impact of transfer molding material on PA module performance.
Critical areas on the module to cause output power (Pout) degradation
were identified, which serves as a guidance for design compensation to
minimize molding effects. Three areas of
study were conducted, focusing on dielectric property characterization
of various transfer molding compounds; EM simulation on output
matching circuits with and without molding, and selective glob top
experiments on various parts of the module.
Biography of
Speaker:
Li Li
is currently a Distinguished Member of Technical Staff at Motorola¡¯s
Semiconductor Products Sector in Tempe, AZ. She received a Ph.D. in
electrical engineering from the State University of New York at
Binghamton, in 1995. She has worked on various areas of packaging
material and process development, including flip chip interconnect and
chip scale package development, Sn-Pb and Pb-free solder wafer
bumping, and anisotropically electrically conductive adhesive
interconnects. She is currently working on RF module development,
component models for design libraries to facilitate effective RF
module design flows, embedded passive filter and matching network
design and simulation, integrated passives design and simulation on
SiGe substrate and organic substrate, and flip chip introduction in RF
modules.
Li Li has
published more than 35 technical papers in the electronic packaging
area. She has three issued US patents and two pending. She has more
than 15 internal Motorola publications, and received three Best Paper
Awards at Motorola¡¯s internal conferences. She is a senior member of
IEEE Society and a member of the CPMT Board of Governors. She was
awarded the IEEE CMPT Society¡¯s ¡°Outstanding Young Engineer Award¡± for
the year 2002 (co-winner). She won the first Motorola-IEEE CPMT
Society Graduate Fellowship Award for Research on Electronic Packaging
in 1993.
Invited Talk 7£ºMaterials
and Processes Issues in Fine Pitch Eutectic Solder Flip Chip
Interconnection
Speaker: C.
Liu†, M.W. Hendriksen*,
D.A. Hutt, P.P. Conway, and D.C. Whalley, Wolfson School of Mechanical
and Manufacturing Engineering Loughborough University, Loughborough,
Leics, LE11 3TU, UK; *Manufacturing
Technology Group, Celestica Limited, West Avenue, Kidsgrove,
Stoke-on-Trent, Staffordshire, ST7 1TL, UK
Abstract:
New product designs within the
electronics packaging industry continue to demand interconnects at
microscopic geometry, both at the Integrated Circuit (IC) and
supporting board level, thereby creating numerous manufacturing
challenges. Flip Chip On Board (FCOB) applications are currently being
driven by competitive manufacturing costs and the need for higher
volume and robust production capabilities. One of today¡¯s low cost
FCOB solutions has emerged as an extension of the existing
infrastructure for Surface Mount Technology (SMT) and combines an
Under Bump Metallisation (UBM) with a stencil printing solder bumping
process, to generate mechanically robust joint structures with low
electrical resistance between chip and board. Although electroless Ni
plating of the UBM, and stencil printing for solder paste deposition,
have been widely used in commercial industrial applications, there
still exists a number of technical issues related to these materials
and processes as the joint geometry is further reduced. This paper
reports on trials with electroless Ni plating and stencil paste
printing and the correlation between process variables in the
formation of bumps and the shear strength of such bumps at different
geometries. The effect of precise control of the tolerances of
squeegees, stencils and wafer fixtures was examined to enable the
optimisation of the materials, processes and tooling for reduction of
bumping defects.
Short
Biography of Speaker:
Dr. Changqing
Liu received his BEng
in Materials Science and Engineering from Nanjing
University of Science and Technology in 1985, and an MSc in Wear
Corrosion and Protection of Metals from the Institute of Metal
Research (IMR) of Chinese Academy of Science in 1988. After five years
of assistant professorship with IMR, he was awarded an Overseas
Research Scholarship (ORS) for his doctoral research in 1993 and
received his PhD degree in Engineering Design and Manufacture from
Hull University, UK. He then started his Postdoctoral Research in the
Interdisciplinary Research Centre (IRC) in Materials of Birmingham
University from 1997. Since 2000 he joined the Wolfson School of
Mechanical and Manufacturing Engineering of Loughborough University as
a Research Fellow. He is a Chartered Engineer of Engineering Council,
UK; and a member of Institute of Electrical and Electronics Engineers,
Inc. (IEEE), CPMT Society, USA; Institute of Materials, Mineral and
Mining (IMMM), UK; Institute of Nanotechnology (IoN), UK; Institute of
Circuit Technology (ICT), UK.
Dr. Liu¡¯s
research is primarily in the area of materials and manufacturing
processes, with particular reference to materials characterisation and
innovative fabrication technologies. He has been involved in a number
of projects concerned with the microstructure and mechanical,
electrochemical and tribological performance of advanced materials and
coatings. Since 2000, his research is centred on the
fine-structure-featured micro-joining technologies to enable the cost
effective, environmentally friendly electronics interconnection with
an emphasis of increasingly diminished joint geometry. His current
research focuses on the materials behaviour in micro-joining in
connection with fabrication technologies, microstructural
characteristics and mechanical integrity of Pb free micro-joints at
micro and nano scale. Dr. Liu has published over 60 refereed papers
including over 30 publications in the peer-reviewed academic journals.
He with his co-authors has won a best paper award in Session 203 at
the 28th IEMT (SEMI, IEEE), San Jose (USA) in July 2003,
and the Cookson Electronics Paper Award at the 5th EMAP
(IEEE/CPMT), Singapore in November 2003.
Invited Talk 8: Microstructure Evolution and Shear Strength of
Eutectic Sn-9Zn and Sn-0.7Cu Lead-Free BGA Solder Balls
Speaker: C.M.L. Wu and C.M.T. Law, Department of Physics and
Materials Science, City University of Hong Kong, Hong Kong SAR.
e-mail: Lawrence.Wu@cityu.edu.hk
Outline of Speech:
Flip-chip and ball grid array (BGA) solder interconnections have
become important technologies in the microelectronic packaging
industry. In some BGA packages, solder balls of about 0.76 mm in size
are used to form solder joints between the metallization pads of the
BGA and the printed circuit board (PCB) for electrical connection. To
enhance good physical connection between solder ball and the die,
under bump metallization (UBM) is usually constructed to receive the
solder balls. The UBM usually has a multilayer structure, e.g.
Au/Ni/Cu layer. The Au and Ni layers, with thickness of about 0.1-1µm
and 5-10µm thick respectively, can be deposited on Cu by
electroplating. The thin Au layer serves as the wetting layer for
soldering and for oxidation protection to the underlying layer. The
thick Ni layer acts as an efficient barrier layer to prevent rapid
reaction between the molten solder and the Cu layer. The Cu layer is
part of the electrical circuit in the BGA package substrate. In view
of the development of lead (Pb)-free solders, their long-term
reliability when used in electronic products is of utmost concern.
Most Pb-free solders are Sn-based and with higher melting point than
that of eutectic Sn-Pb of 183oC. This simply means that Pb-free
solders are reflowed at higher temperatures than that of Sn-Pb,
leading to faster growth of intermetallic compounds (IMCs) at the
interface between the solder balls and the UBM of the BGA. The
formation of the IMCs at the interface is required to provide solder
joint strength [3-6]. However, as the IMC is brittle, if the IMC layer
(IML) is excessively thick, then it will have an adverse effect on the
strength of a solder joint, and may result in early failure of the BGA
package.
The eutectic Sn-9Zn solder alloy has been regarded as a possible
substitute for eutectic Sn-37Pb alloy because its eutectic temperature
(199oC) is very close to that of the eutectic Sn-37Pb. The eutectic
Sn-0.7Cu solder alloy is cheap and possesses good solderability,
strength and creep properties.
To demonstrate their feasibility to be used as BGA solder bumps,
Sn-9Zn and Sn-0.7Cu solder balls are attached on the UBMs of a BGA
substrate, so that the interfacial microstructure evolution can be
studied. Also, the thermal reliability of the Pb-free BGA solder bump
is demonstrated by thermal aging at 150oC for up to 1000 hr.
In the as-reflowed Sn-9Zn solder bump, its bulk microstructure mainly
contains the ¦Â-Sn matrix, and scattered with Zn-rich and AuSn4
compounds. Au-Zn intermetallic compounds (IMCs) were found near the
solder/UBM interface, at which a Ni-Zn-Sn ternary IMC layer of about
1¦Ìm thick was detected. Upon aging at 150oC, NiZn3 ¦Ã phase and Au-Zn
IMCs were formed quite close to the Ni-Zn-Sn IML. Further aging
provided a NiZn3 layer on top of the original Ni-Zn-Sn IML. The Zn
content in the Ni-Zn-Sn ternary layer increased with aging time.
The as-reflowed bulk microstructure of the Sn-Cu solder bump has
Cu6Sn5 and AuSn4 segregated along the ¦Â-Sn boundary. At the interface,
Cu-Sn-Ni ternary intermetallic layer was formed. After aging, AuSn4
was coarsened, and the Cu-Sn-Au phase was detected in the bulk solder
and at the interface. The Cu-Sn-Ni layer at the interface was
thickened due to aging.
The shear strength of the two types of Pb-free BGA bumps were found to
be higher than that of Sn-37Pb.
Biography of Speaker:
Dr Lawrence Wu graduated from the University of Bristol, U.K. in
Aeronautical Engineering with First Class Honours. He also obtained
his PhD from the same university. He has been working at City
University of Hong Kong (CityU) since 1987. He is currently an
Associate Professor at the Department of Physics and Materials
Science. He is also the Deputy Director of the Centre for Electronic
Packaging and Assemblies, Failure Analysis and Reliability Engineering
at CityU.
Dr Wu has been conducting research on lead-containing and lead-free
alloys for a number of years, in particular on surface mount solder
joint strength, lead-free solder development, and the formation and
analysis of lead-free solders doped with rare earth elements.
Apart from lecturing on the courses of ¡°electronic packaging and
materials¡± and ¡°failure analysis and cases studies¡± at senior
undergraduate and postgraduate levels at CityU, he is also active in
conducting failure investigation/analysis and materials
characterization related to industries.
1
2
3
